Recently, in semiconductor devices including a multilayer wiring film provided on a silicon substrate, with the miniaturization of the wiring and wiring spacing, a low dielectric film (low-k film) has been used for the inter-layer insulating film. However, in general, the low dielectric film has low adhesiveness to the metal wiring. Therefore, there is a problem in which the inter-layer insulating films are peeled apart from each other due to chipping impact in the dicing process and the thermal stress applied after packaging.
To solve this problem, there is proposed a technique in which a vertical structure body made of wirings and vias is provided in the circumferential region of the chip. The vertical structure body is a structure in which wirings and vias are vertically connected in the inter-layer insulating film (see, e.g., JP-A 2004-235357 (Kokai)).